Research on Efficient Vision-Based Hardware Architecture for Feature Representation and Object Detection

Research on Efficient Vision-Based Hardware Architecture for Feature Representation and Object Detection (特徴表現及び物体検出のための効率的なビジョンベースのハードウェアアーキテク チャに関する研究)Machine learning (ML) is described by Arthur Samuel as the field of study that gives computers the ability to learn without being explicitly programmed.The methods for solving ML problem can be classified into two groups, i.e. supervised learning and unsupervised learning.Pattern recognition is a branch of ML that focuses on the recognition of patterns and regularities in data.Pattern recognition systems can be trained from labeled training data in supervised learning, but also can be used to discover previously unknown patterns in unsupervised learning when no labeled data are available.Feature representation is becoming an important prerequisite for building ML models to achieve high detection performance, in particular in vision-based applications.A wealth of feature-extraction techniques are being presented in this research field.To meet for the embedded systems with limited resources, this thesis developed a simplified scale -invariant speeded up robust features (SURF) approach, which can decrease object-matching complexity and enhance computational performance significantly, to extract the feature vectors in the image.Whereas, the histogram of oriented gradient (HOG) is a widely accepted feature for object detection, which attains high accuracy against changes of illumination of variously textured objects.Comparing to hardware solutions, the software technologies for feature extraction are more affected by computationally demanding algorithms so that the power dissipation of so ftware technologies is burdensome for mobile applications and the processing speed becomes a bottleneck in case of real-time (>30 frames/s) object detection.Consequently, the achievable advantages of faster processing speed and lower power consumption lead to application-specific integrated circuit (ASIC) solutions.Therefore, a resource-efficient coprocessor for a simplified SURF descriptor, employing Haar-like wavelets as feature vectors (FVs), is developed and a prototype is fabricated in 180nm CMOS technology in this research.A pipelined hardware architecture with the low computational budget, that directly uses the serially-inputted pixel data without pre-storage, is